1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming replacement spacer structures on a semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Typically, a high performance integrated circuit product, such as a high performance microprocessor, will contain billions of individual field effect transistors (FETs). The transistors are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region of the transistor. The transistor devices come in a variety of forms, e.g., so-called planar transistor devices, 3D or FinFET devices, etc.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid so-called short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in such metal gate structures. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in metal gate structures so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), etc. One well-known processing method that has been used for forming a transistor with a metal gate structure is the so-called “gate-last” or “replacement gate” technique. The replacement gate process may be used when forming planar devices or 3D devices. At a very high level, the replacement gate process involves: (1) forming a sacrificial or dummy gate structure above a substrate with a cap layer positioned thereabove; (2) forming sidewall spacers adjacent the sacrificial gate structure; (3) forming source/drain regions for the device (which may include the formation of epi semiconductor material in the source/drain regions of the device); (4) forming a layer of insulating material across the device; (5) removing the gate cap layer positioned above the sacrificial gate structure; (6) removing the sacrificial gate structure so as to define a gate cavity; (7) forming a replacement metal gate structure in the gate cavity; and (8) forming a gate cap layer above the replacement metal gate structure.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end that is connected to a respective metal line in the metallization layer by a conductive via. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. As the critical dimensions of the circuit elements in the device level decreased, the dimensions of metal lines, vias and contact elements were also reduced.
Typically, spacers on newer technology devices are made of a material having a dielectric constant (k) value that falls within the range of about 5 to 5.5, such as SiCN, SiBN, etc. However, it would be desirable to use a spacer having a lower k value to reduce the parasitic capacitance between the gate structure and the source/drain contact. For example, making the spacers from silicon dioxide (k value of about 3.9) would reduce the gate-tocontact capacitance and reduce the AC delay of a circuit. However, a silicon dioxide spacer is not compatible with current replacement gate (RMG) processing techniques that include a wet clean process or with self-aligned contact (SAC) etch processing flows. One prior technique that has been employed in an effort to obtain a silicon dioxide spacer that is not subjected to damage during the RMG gate pre-clean process or the typical SAC contact etch processing sequence is described below in FIGS. 1A-1F.
FIGS. 1A-1F schematically illustrate an illustrative prior art transistor device and various problems that may arise when forming conductive contacts to such a device. As shown in FIG. 1A, the device 10 is formed above an active region that is defined in a semiconductor substrate 12 by an isolation structure (not shown), such as a shallow trench isolation structure. The device 10 includes a gate structure comprised of a gate insulation layer 13, a gate electrode 14, a gate cap layer 16, sidewall spacers 18, a layer of insulating material 22 and raised source/drain regions 20. The sidewall spacers 18 and the gate cap layer 16 are typically made of silicon nitride, while the layer of insulating material 22 is typically made of silicon dioxide.
As shown in FIG. 1B, a contact etching process was performed to define a contact opening 24 in the layer of insulating material 22. Although a single contact opening 24 is depicted in the figures, those skilled in the art will appreciate that there will be another such contact opening 24 formed on the opposite side of the gate structure. As part of this contact etching process, after the contact opening 24 is formed in the layer of insulating material 22, a brief “punch through” etch process is typically performed to remove a very thin underlying silicon nitride layer (not shown)—a so-called contact etch stop layer—that is positioned above the source/drain regions. As depicted in the dashed-line region 26, some of the spacer 18 is consumed during one or both of these etching processes. Moreover, an isotropic etching process is typically performed to insure that all of the relatively higher k value silicon nitride spacer material is removed from the gate sidewall prior to the formation of the more desirable low-k spacer. The spacer 18 and the gate cap layer 16 serve a vital role in protecting the gate structure from damage during subsequent processing operations. FIG. 1C depicts an illustrative situation wherein substantially all of the spacer 18 and a portion of the gate cap layer 16 were removed during the contact etching process. As depicted in the dashed-line region 28, in this situation, portions of the gate structure 13, 14 may be exposed.
In an attempt to avoid the situation depicted in FIG. 1C, device manufacturers have formed single sidewall spacers 30 (see FIG. 1D) in the contact opening 24 to insure that the gate structure is protected. The spacers 30 may be formed by conformably depositing a layer of spacer material and thereafter performing an anisotropic etching process.
In the embodiment shown in FIGS. 1B-1D, the contact opening 24 is substantially properly aligned (or only slightly misaligned) in comparison to the intended location of the contact opening 24 relative to the location of the source/drain region 20 and the gate structure of the device 10. FIGS. 1E-1F depict an embodiment wherein a contact opening 24A is substantially misaligned in comparison to the intended location of the contact opening 24A relative to the location of the source/drain region 20 and the gate structure of the device 10. More specifically, after formation of the contact opening 24A, a significant portion of the gate structure may be exposed in the region indicated by the arrow 19. In FIG. 1F, the above-described prior art processing technique was performed in an effort to form spacers 30 in the contact opening 24A to protect the gate structure. However, due to the significant misalignment of the opening 24A, and the nature of the manner in which the spacers 30 are formed, two separate spacers 30A, 30B are formed above and adjacent the gate structure, respectively. Due to the significant misalignment of the contact opening 24A, portions of the gate structure may remain exposed, as depicted in the dashed-line region 32, or have only a very minimal amount of spacer material protecting the gate structure in subsequent processing operations. Such a situation can lead to undesirable electrical short circuits that can effectively destroy the functionality of an electronic circuit that includes such a transistor device.
The present disclosure is directed to various methods of forming replacement spacer structures on a semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.